LDMOS devices are widely used electronic devices, especially in applications requiring significant power handling capability and as output devices. One of the limitations of LDMOS and similar devices is their sensitivity to electrostatic discharge and similar transients, collectively referred to herein by the acronym “ESD”. It is known to use various shunting devices across the output of LDMOS and other semiconductor devices to clamp the voltage appearing thereon to a level below the destructive breakdown voltage of the device. Zener diodes and various types of parasitic semiconductor devices are often employed for this purpose. While such devices may some provide ESD protection for LDMOS devices, they suffer from a number of limitations. For example, the current handling capability of a protective ESD device may be inadequate, it may consume too much area on the device or integrated circuit (IC), it may require a different processing technology that what is used to build the rest of the device or IC, the response time of the ESD device may be too slow to protect against fast transients, the ESD device may show undesirable aging wherein its ability to sustain further transients slowly degrades with time, the properties of the ESD device may undesirably vary with fluctuations inherent in the manufacturing process thereby reducing the overall yield of good devices or ICs, the ESD device may interfere with normal operation of the device or IC it is intended to protect, and so forth. All of these and other limitations may be encountered, depending upon the type of ESD protection device intended to be employed with a particular IC or power device and the semiconductor processing and device technology being used. Accordingly, there is an ongoing need for improved ESD protection devices, especially for use with LDMOS devices and particularly with open-drain LDMOS devices.
Accordingly, it is desirable to provide improved ESD protection for semiconductor devices, especially for LDMOS devices. It is desirable that the means and method for providing ESD protection be process insensitive, that is, the ESD devices be equally or less susceptible to manufacturing process variations than the device or IC being protected. In addition, it is desirable that the means and method for providing ESD protection not require additional and/or more costly manufacturing steps or add a significant area burden to the IC or device being protected. In addition, it is desirable that the ESD device has electrical properties generally compatible with the device or circuit being protected. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.